1. Field of the Invention
The present invention relates to the field of manufacture of integrated circuits, and, more particularly, to the formation of contact plugs requiring a multi-level etch procedure as is the case, for example, for substrate contacts and device contacts of circuit elements formed on an insulating substrate, such as silicon-on-insulator (SOI) devices.
2. Description of the Related Art
In modern integrated circuits, the number and, hence, the packing density of circuit elements, such as field effect transistors, is steadily increasing and, as a consequence, performance of these integrated circuits is currently improving. The increase in packing density and signal performance of integrated circuits requires the reduction of critical feature sizes, such as the gate length and, thus, the channel length, of field effect transistors to minimize the chip area occupied by a single circuit element and to reduce signal propagation delay owing to a delayed channel formation. However, currently, critical feature sizes are approaching 0.1 μm and less and a further improvement in circuit performance by reducing the sizes of the transistor elements is partially offset by parasitic capacitances of the transistors formed in bulk silicon substrates.
In order to meet the ever-increasing demands with respect to device and circuit performance, circuit designers have proposed new device architectures. One technique to improve performance of a circuit, for example of a CMOS device, is to manufacture the circuit on a so-called silicon-on-insulator (SOI) substrate, wherein an insulating layer is formed on a bulk substrate, for example a silicon substrate or glass substrate, wherein the insulating layer frequently comprises silicon dioxide (also referred to as a buried oxide layer). Subsequently, a silicon layer is formed on the insulating layer in which an active region for a field effect transistor device is defined by shallow trench isolations. A correspondingly fabricated transistor is electrically entirely isolated from the regions surrounding the transistor area. Contrary to a conventional device formed on a bulk semiconductor substrate, the precise spatial confinement of the active region of the SOI device significantly suppresses parasitic effects known from conventional devices, such as latch-up and leakage currents drifting into the substrate. Moreover, SOI devices are characterized by lower parasitic capacitances compared to devices formed on a bulk semiconductor substrate and, hence, exhibit an improved high frequency performance. Furthermore, due to the significantly reduced volume of the active region, radiation-induced charge carrier generation is also remarkably reduced and renders SOI devices extremely suitable for applications in radiation-intensive environments.
On the other hand, the advantages of SOI devices over conventionally fabricated devices may partially be offset by the so-called floating body effect, wherein the substrate of the device is not tied to a defined potential, which may lead to an accumulation of charge carriers, thereby adversely affecting the transistor characteristics, such as the threshold voltage, single-transistor-latch-up, and the like. Therefore, so-called substrate contacts are frequently formed to provide a connection to the substrate to drain off the excess charge.
With reference to FIGS. 1a and 1b, a typical conventional process flow for forming a substrate contact and contacts to a circuit element will now be described in more detail. In FIG. 1a, a semiconductor device 100 is schematically shown in a cross-sectional view. The semiconductor device 100 comprises an SOI substrate 101, which in turn includes a crystal-line silicon layer 102 that is typically provided in the form of a bulk silicon substrate with an insulation layer 103 formed thereon. The insulation layer 103 may often be referred to as a buried oxide layer, since, typically, the insulating layer 103 may be comprised of silicon dioxide. However, the insulating layer 103 may include other insulating materials, such as silicon nitride and the like, depending on the process for forming the SOI substrate 101. The SOI substrate 101 further includes a semiconducting layer 104 having a thickness that allows the formation of circuit elements such as a field effect transistor 110. The semiconducting layer 104 may be formed from a variety of materials, e.g., crystalline silicon, silicon-germanium, or any III-V and II-VI semiconductors in crystalline form, etc.
The field effect transistor 110 is enclosed by a trench isolation structure 105 that includes an insulating material, such as silicon dioxide and/or silicon nitride. For convenience sake, merely one cross-section of the trench isolation structure 105 is depicted. Thus, the field effect transistor 110 is formed on a respective silicon island that may be completely insulated from other circuit elements by the trench isolation structure 105 and the insulating layer 103. The field effect transistor 110 may include a gate electrode 111 that is separated from a channel region 113 by a gate insulation layer 112. Moreover, drain and source regions 114 may be provided within the silicon layer 104 and sidewall spacers 115 may be located at sidewalls of the gate electrode 111. The channel region 113, the drain and source regions 114 and the gate electrode 111 may comprise a dopant material with an appropriate concentration so as to provide the desired electrical performance of the transistor 110. Moreover, metal silicide regions (not shown) may be formed on top of the source and drain regions 114 and the gate electrode 111 to minimize the resistance of these regions.
The semiconductor device 100 further comprises a dielectric layer 107, wherein a thickness of the dielectric layer 107 is selected such that the transistor 110 is completely embedded within the dielectric layer 107. The dielectric layer 107 may be comprised of silicon dioxide. In some cases, a thin dielectric layer (not shown) may be provided between the dielectric layer 107 and the transistor 110. Typically, the composition and thickness of this optional dielectric layer may be selected so as to act as a bottom anti-reflective coating in a subsequent lithography process for forming contacts to the transistor 110 and to the silicon layer 102 of the SOI substrate 101. Moreover, the optional dielectric layer may act as an etch stop layer during the formation of the contact openings. A resist layer 108 is formed above the dielectric layer 107 and has openings 109 with dimensions that substantially represent the dimensions of corresponding contact openings to be formed.
A typical process flow for manufacturing the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. The SOI substrate 101 may be formed by sophisticated wafer bonding techniques and may be purchased from corresponding manufacturers in a condition that allows the subsequent formation of the transistor 110. Then, the trench isolation structure 105 may be formed by well-established photolithography, etch and deposition techniques to define a lithography resist mask, etch respective trenches, and subsequently deposit one or more insulating materials to fill the trenches, thereby forming the trench isolation structure 105. Thereafter, any excess material may be removed by chemical mechanical polishing (CMP), thereby also planarizing the substrate surface. Afterwards, the gate insulation layer 112 may be formed by sophisticated oxidation and/or deposition processes as are well known in the art. Subsequently, the gate electrode 111 may be formed by well-known lithography and etch techniques and implantation cycles may be carried out so as to form the drain and source regions 114 with a required dopant profile, wherein, depending on the process sequence used, the spacer elements 115 may be formed prior, during or after the implantation sequence. The implanted dopants are then activated and lattice damage is cured by anneal cycles with a specified temperature and duration.
Then, metal silicide portions may be formed in the drain and source regions 114 and the gate electrode 111 by well-established silicidation processes. After the completion of the transistor 110, the optional dielectric layer may be deposited, for instance by chemical vapor deposition (CVD), wherein a thickness and a material composition is selected so as to provide the required optical characteristics and/or the desired etch selectivity to the dielectric layer 107 in a subsequent anisotropic etch process. Thereafter, the dielectric layer 107 may be deposited and may be planarized by CMP to provide for a substantially planar surface. Next, the resist layer 108 is formed and patterned in accordance with well-established photo-lithography techniques to define the openings 109.
Subsequently, an etch process sequence is performed to create contact openings in the dielectric layer 107 that connect to the gate electrode 111 and the drain or source region 114, and to create a substrate contact opening that connects to the silicon layer 102. To this end, in one typical approach, an anisotropic etch process is carried out to commonly form the contact openings in the dielectric layer 107, wherein the anisotropic etch process is substantially stopped at or within the optional dielectric layer, if provided. Alternatively, if the optional dielectric layer is not provided or if an anisotropic etch process recipe is used that does not exhibit a specific selectivity between the dielectric layer 107 and the optional dielectric layer, the process may be designed to exhibit a significant selectivity between silicon and silicon dioxide to stop the etch process in the gate electrode 111 and the source region 114, thereby possibly removing silicide prior to reaching the doped polysilicon and the crystalline silicon, respectively, while the etch process in the trench isolation structure 105, substantially comprised of silicon dioxide, still proceeds until the silicon layer 102 is reached. Irrespective of the etch scheme selected, at least during the etch of the lower portion of the substrate contact opening, a high selectivity between silicon and silicon dioxide is required. Thereafter, the resist layer 108 is removed, for example by plasma etching and a subsequent wet chemical clean process. Hence, the process for forming the substrate contact opening and transistor contact openings requires an etch procedure through a plurality of layers, thereby rendering the contact etch quite complex. Therefore, a great burden is placed on the selective etch process so as to reliably define the corresponding contact openings in a common etch process, thereby restricting process margins and reducing yield of the etch process.
FIG. 1b schematically shows the semiconductor device 100 after the above-described sequence is completed. Thus, the semiconductor device 100 comprises a substrate contact opening 120, a gate contact opening 121 and, for example, one contact opening 122 connecting to the source region 114 of the transistor 110. Subsequently, the openings 120, 121 and 122 may be filled with a highly conductive material, such as tungsten, which is presently considered a preferred candidate for a contact metal of high-end, copper-based devices due to the superior thermal stability of tungsten compared to, for example, aluminum, to connect circuit elements to further metallization layers (not shown) of the semiconductor device 100. The tungsten may be filled in by well-established deposition techniques, such as chemical and physical vapor deposition techniques. Thereafter, excess tungsten is removed by a CMP (chemical mechanical polishing) process, thereby also planarizing the substrate surface for the further processing of the device 100 so as to form one or more metallization layers.
Thus, a highly conductive contact to the substrate is achieved, requiring, however, a highly selective etch procedure for commonly defining all of the contact openings, thereby rendering the conventional approach non-efficient in view of reliability.
Due to the plurality of superior characteristics of SOI devices compared to devices formed on bulk silicon substrates and due to the availability of SOI substrates at low cost having silicon layers formed thereon with high quality, the development of SOI devices will gain in importance. Thus, an urgent need exists for an improved contact etch technique that allows the formation of multi-level contacts, for example, including a substrate contact, while eliminating or at least reducing one or more of the above-identified problems concerning a reliable multi-level etch process.